Static random access memories (SRAM) are well known in the art and are formed in a great variety of different structures. Generally, an SRAM is a structure which is bistable, or has two operating points, and which functions equally well in either of the operating points. Further, the SRAM must be capable of being easily switched between the two operating points and must include some means of sensing in which operating point the SRAM is functioning.
SRAMs have been disclosed by Fujitsu Limited which include a double-emitter resonant-tunneling hot electron transistor (RHET) or two resonant-tunneling diodes stacked on a single barrier tunneling diode. The structures are fabricated by epitaxially growing a plurality of layers on an indium-phosphide (InP) substrate. The resonant tunneling barriers are formed by sandwiching an indium-gallium-arsenide (InGaAs) layer between aluminum-arsenide (AlAs) barriers. A collector barrier is formed of indium-aluminum-arsenide (InAlAs).
This type of SRAM has the advantages of being extremely small and utilizing substantially fewer transistors, or active devices, than conventional transistor SRAMs. The major problem with these structures is the fact that memory cells formed in this fashion have relatively larger power consumption and slower speed because of small peak-to-valley current ratios.
Accordingly, it is a purpose of the present invention to provide a new and improved SRAM.
It is a further purpose of the present invention to provide a SRAM with the advantages of being extremely small and utilizing substantially fewer transistors, or active devices, than conventional transistor SRAMs and which has substantially improved speed/power ratio.
It is another purpose of the present invention to provide a SRAM which is relatively simple to fabricate.